TxFIFOEmpty_Sel=TxFIFOEmpty_Sel_0, TxFIFO_Ctrl=TxFIFO_Ctrl_0, RxFIFO_Off_On=RxFIFO_Off_On_0, TxAutoSync=TxAutoSync_0, USrc_Sel=USrc_Sel_0, RxFIFO_Ctrl=RxFIFO_Ctrl_0, RxFIFOFull_Sel=RxFIFOFull_Sel_0, RxFIFO_Rst=RxFIFO_Rst_0, RxAutoSync=RxAutoSync_0, ValCtrl=ValCtrl_0, TxSel=TxSel_0
SPDIF Configuration Register
| USrc_Sel | no description available 0 (USrc_Sel_0): No embedded U channel 1 (USrc_Sel_1): U channel from SPDIF receive block (CD mode) 3 (USrc_Sel_3): U channel from on chip transmitter |
| TxSel | no description available 0 (TxSel_0): Off and output 0 1 (TxSel_1): Feed-through SPDIFIN 5 (TxSel_5): Tx Normal operation |
| ValCtrl | no description available 0 (ValCtrl_0): Outgoing Validity always set 1 (ValCtrl_1): Outgoing Validity always clear |
| DMA_TX_En | DMA Transmit Request Enable (Tx FIFO empty) |
| DMA_Rx_En | DMA Receive Request Enable (RX FIFO full) |
| TxFIFO_Ctrl | no description available 0 (TxFIFO_Ctrl_0): Send out digital zero on SPDIF Tx 1 (TxFIFO_Ctrl_1): Tx Normal operation 2 (TxFIFO_Ctrl_2): Reset to 1 sample remaining |
| soft_reset | When write 1 to this bit, it will cause SPDIF software reset |
| LOW_POWER | When write 1 to this bit, it will cause SPDIF enter low-power mode |
| TxFIFOEmpty_Sel | no description available 0 (TxFIFOEmpty_Sel_0): Empty interrupt if 0 sample in Tx left and right FIFOs 1 (TxFIFOEmpty_Sel_1): Empty interrupt if at most 4 sample in Tx left and right FIFOs 2 (TxFIFOEmpty_Sel_2): Empty interrupt if at most 8 sample in Tx left and right FIFOs 3 (TxFIFOEmpty_Sel_3): Empty interrupt if at most 12 sample in Tx left and right FIFOs |
| TxAutoSync | no description available 0 (TxAutoSync_0): Tx FIFO auto sync off 1 (TxAutoSync_1): Tx FIFO auto sync on |
| RxAutoSync | no description available 0 (RxAutoSync_0): Rx FIFO auto sync off 1 (RxAutoSync_1): RxFIFO auto sync on |
| RxFIFOFull_Sel | no description available 0 (RxFIFOFull_Sel_0): Full interrupt if at least 1 sample in Rx left and right FIFOs 1 (RxFIFOFull_Sel_1): Full interrupt if at least 4 sample in Rx left and right FIFOs 2 (RxFIFOFull_Sel_2): Full interrupt if at least 8 sample in Rx left and right FIFOs 3 (RxFIFOFull_Sel_3): Full interrupt if at least 16 sample in Rx left and right FIFO |
| RxFIFO_Rst | no description available 0 (RxFIFO_Rst_0): Normal operation 1 (RxFIFO_Rst_1): Reset register to 1 sample remaining |
| RxFIFO_Off_On | no description available 0 (RxFIFO_Off_On_0): SPDIF Rx FIFO is on 1 (RxFIFO_Off_On_1): SPDIF Rx FIFO is off. Does not accept data from interface |
| RxFIFO_Ctrl | no description available 0 (RxFIFO_Ctrl_0): Normal operation 1 (RxFIFO_Ctrl_1): Always read zero from Rx data register |